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1 pf1052-02 E0C63P366 4-bit single chip microcomputer l function evaluation flash built-in l compatible with e0c63358 and 158 l on-board writing supported n description the E0C63P366 is a cmos 4-bit microcomputer composed of a 4-bit cmos core cpu, rewritable rom (flash), ram, segment lcd driver, serial interface and timers. the E0C63P366 has a built-in large-capacity flash rom (16k 13 bits) and a ram (2,048 4 bits), and is upper compatible with the e0c63358 and e0c63158. the E0C63P366 can be used as a mtp (multi-time programming) when developing programs. n features l cmos lsi 4-bit parallel processing ..... e0c63000 core cpu l osc1 oscillation circuit ......................... 32.768khz (typ.) crystal oscillation l osc3 oscillation circuit ......................... 1.8mhz (typ.) cr oscillation / 4mhz (max.) ceramic oscillation ( * 1) l instruction set ........................................ basic instruction : 46 types (411 instructions with all) addressing mode : 8 types l instruction execution time ..................... during operation at 32.768khz : 61sec (min.) during operation at 4mhz : 0.5sec (min.) l rom (flash) capacity ........................... code rom : 16,384 words 13 bits segment option rom : 2,048 words 4 bits programming method : parallel and serial programming l ram capacity ........................................ data memory : 2,048 words 4 bits display memory : 32 words 4 bits l input port ............................................... 9 bits 8 bits (with pull-up resistors) 1 bit (for key position sensing interrupt by a/d) l output port ............................................ 12 bits (2 special outputs are available * 2) l i/o port .................................................. 20 bits (4 serial inputs/outputs are available * 2) (4 a/d inputs are available * 2) l serial interface ...................................... 1 port (8-bit clock synchronous system) l lcd driver ............................................. 32 segments 4 / 3 / 2 commons ( * 2), 1/3 bias drive l time base counter ................................ 1 line (clock timer) l programmable timer ............................. built-in (8 bits 2 ch. or 16 bits 1 ch.) l watchdog timer ..................................... built-in l a/d converter ........................................ 8-bit resolution maximum error : 3lsb, a/d clock : osc1, osc3 (2.7v to 5.5v) l buzzer output ........................................ buzzer frequency : 2khz or 4khz ( * 2), 2hz interval output ( * 2) l supply voltage detection (svd) circuit .. 2.7v or 2.8v ( * 2) l interrupts ............................................... external : input port interrupt 2 lines key sensing interrupt 1 line internal : clock timer interrupt 4 lines programmable timer interrupt 2 lines serial interface interrupt 1 line a/d converter interrupt 1 line
2 E0C63P366 l supply voltage ...................................... 2.7 to 5.5v l operating temperature .......................... -20 to 70c l current consumption (typ.) .................. single clock halt mode (32khz) 3v (lcd power off) 2.5a 3v (lcd power on) 37a operating mode (32khz) 3v (lcd power on) 120a twin clock operating mode (4mhz) 3v (lcd power on) 800a l package ................................................ qfp15-100pin or die form * 1: can be selected with mask option * 2: can be selected with software n block diagram * the prom block indicate with a dotted line, the ram block and the svd circuit differ from the e0c63358/e0c63158. osc1 osc2 osc3 osc4 sprg rxd txd sclk clkin com0~3 seg0~31 v dd v c1 ~ 3 ca~cb v d1 v ss bz k00~k03 k10~k13 k20 test reset p00~p03 p10~p13 p20~p23 p30~p33 p40~p43 r00~r03 r10~r13 r20~r23 av dd av ss av ref core cpu e0c63000 code rom (flash) 16,384 words 13 bits prom programmer system reset control interrupt generator osc ram 2,048 words 4 bits segment option rom (flash) 2,048 words 4 bits lcd driver 32 seg 4 com power controller svd buzzer output clock timer serial interface programmable timer/counter input port a/d i/o port output port
3 E0C63P366 n prom programming and operating mode the E0C63P366 has built-in flash eeproms as the code rom and the segment option rom that allow the developer to program the rom data using the exclusive prom writer (universal rom writer ii). to create data to be written to the code rom, use the e0c63 assembler similar to the e0c63358/e0c63158. to create data to be written to the segment option rom use the segment option generator sog63358 similar to the e0c63358. refer to "e0c63358 development tool manual", for the sog63358. this section explains the prom programmer that controls data writing and the writing mode. l configuration of prom programmer the configuration of the prom programmer is shown below. serial transfer controller code rom programming control circuit parallel transfer controller v dd v ss rxd txd sclk clkin address data control signal sprg segment option rom prom programmer prom block exclusive prom writer the prom programmer supports the following two writing modes. 1) serial programming 2) parallel programming serial programming mode uses the serial communication ports of the prom writer and E0C63P366 to write data. this mode enables on-board programming by designing the target board with a serial writing function. in parallel programming mode, the on-chip flash rom can be directly programmed using the exclusive prom writer with the adaptor socket installed. refer to "operating mode" for each programming method. terminals the E0C63P366 provides the following terminals for programming the flash eeprom. sprg flash programming control terminal (pull-up resistor built-in) when set to high normal operation mode (the cpu executes the program in the flash eeprom.) when set to low programming mode (for writing data to the flash eeprom) sclk serial transfer clock input/output terminal for serial programming (pull-up resistor built-in) rxd serial data input terminal for serial programming (pull-up resistor built-in) txd serial data output terminal for serial programming clkin prom programmer clock input terminal (1mhz; pull-up resistor built-in) the five terminals above are provided exclusively for the flash eeprom. the e0c63358 and e0c63158 do not have these terminals.
4 E0C63P366 l operating mode three operating modes are available in the E0C63P366: one is for normal operation and the others are for programming. the operating mode is decided by the terminal settings at power-on or initial reset. when the sprg terminal is set to low, the E0C63P366 enters serial programming mode. to operate the E0C63P366 in normal operation mode (to execute the instruction written to the flash eeprom after program- ming), the sprg terminal should be set to high or open. the parallel programming including the mode switching and terminal settings is controlled by the exclusive prom writer. the following table lists the operating modes. operating mode normal operation mode serial programming mode parallel programming mode sprg terminal high or open low set by the prom writer normal operation mode in this mode, the e0c63000 core cpu and the peripheral circuits operate by the instructions programmed in the flash eeprom. the flash eeprom bit data is set to "1" at shipment. in normal operation mode, set the terminals for programming the flash eeprom as below. the board must be designed so that the terminal settings cannot be changed while the ic is operating. terminal sprg sclk rxd txd clkin set-up high (external switch) high or open high or open open high or open serial programming mode serial programming mode writes data to the flash eeprom using a serial communication between the exclu- sive prom writer (universal rom writer ii) and the E0C63P366. by providing a serial communication port on the target board, the E0C63P366 on the board can be programmed (on-board writing). terminal sprg sclk rxd txd clkin v ss reset set-up low (external switch) connected to the prom writer connected to the prom writer connected to the prom writer connected to the prom writer connected to the prom writer connected to an external switch when the sprg terminal is set to low, the E0C63P366 starts operating in serial programming mode after power-on or an initial reset. be sure not to change the sprg terminal status during normal operation or serial programming, because the operating mode may change according to the terminal status. the sprg terminal must be switched while the reset terminal is set to low. the serial programming is performed using the 1mhz clock supplied from the prom writer to the clkin terminal. take noise measure into consideration so that noise does not affect the clock line input to the clkin terminal when designing the target board.
5 E0C63P366 the prom writer does not supply the source voltage to the E0C63P366 during serial programming. therefore, supply a 5v source voltage between the v dd and v ss terminals of the E0C63P366 in order to operate the osc1 oscillation circuit. furthermore, to start a serial programming, an initial reset to the E0C63P366 is required. use the reset termi- nal to reset the E0C63P366 securely after turning the prom writer on. the following shows the timing chart to start serial programming mode. reset sprg 0.5? s prom writer power on start serial programing mode parallel programming mode the parallel programming can be performed by installing the E0C63P366 to the exclusive prom writer via the adaptor socket. in this mode, it is not necessary to set up the programming terminals since it is controlled by the exclusive prom writer.
6 E0C63P366 n differences from the mask rom models this section explains the differences in functions (except for the flash eeprom block) between the E0C63P366 and the mask rom models (e0c63358 and e0c63158). l mask option the mask option items are fixed in the E0C63P366 as shown in the table below. mask option osc1 oscillation circuit osc3 oscillation circuit multiple key reset combination multiple key reset time authorize input port pull-up resistors k00 k01 k02 k03 k10 k11 k12 k13 k20 output port output specifications r10?13 r20?23 i/o port output specifications p10?13 p20 p21 p22 p23 p30 p31 p32 p33 p40 p41 p42 p43 i/o port pull-up resistors p10?13 p20 p21 p22 p23 p30 p31 p32 p33 p40 p41 p42 p43 lcd drive bias serial interface signal polarity buzzer output specification setting 1 crystal (32.768 khz) ceramic not used not used with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor no pull-up resistor no pull-up resistor no pull-up resistor no pull-up resistor 1/3 bias (internal) negative polarity positive polarity setting 2 crystal (32.768 khz) cr not used not used with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output complementary output with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor with pull-up resistor no pull-up resistor no pull-up resistor no pull-up resistor no pull-up resistor 1/3 bias (internal) negative polarity positive polarity
7 E0C63P366 l power supply since the E0C63P366 is produced using the flash eeprom process, the characteristics are different from those of the mask rom models. 1) operating voltage range E0C63P366: 2.7 to 5.5v e0c63358: 2.3 to 3.6v (min. 0.9v when the osc3 is not used) e0c63158: 2.3 to 3.6v (min. 0.9v when the osc3 is not used) the circuit blocks of the E0C63P366 except for the oscillation circuit and lcd driver (cpu, rom, ram and peripheral digital circuits) operate with the source voltage supplied between the v dd and v ss terminals. therefore, the vdc register (i/o memory address: ff00h, data bit: d0) is invalidated and is used as a gen- eral-purpose register. writing "1" or "0" to this register does not affect the v d1 output voltage level. address comment d3 d2 register d1 d0 name init 1 0 ff00h clkchg oscc 0 vdc r r/w r/w clkchg oscc 0 vdc 0 0 0 osc3 on 2.25 v osc1 off 1.35 v cpu clock switch osc3 oscillation on/off unused cpu operating voltage switch (1.35 v: osc1, 2.25 v: osc3) e0c63358 address comment d3 d2 register d1 d0 name init 1 0 ff00h clkchg oscc 0 vdc r r/w r/w clkchg oscc 0 vdc 0 0 0 osc3 on 2.1 v osc1 off 1.3 v cpu clock switch osc3 oscillation on/off unused cpu operating voltage switch (1.3 v: osc1, 2.1 v: osc3) e0c63158 address comment d3 d2 register d1 d0 name init 1 0 ff00h clkchg oscc 0 vdc r r/w r/w clkchg oscc 0 vdc 0 0 0 osc3 on 1 osc1 off 0 cpu clock switch osc3 oscillation on/off unused general-purpose register E0C63P366 * in the E0C63P366, the v d1 level is fixed at 2.05v regard less of the vdc register value. 2) operating mode of oscillation system voltage regulator the operating mode range of the E0C63P366 is different from that of the e0c63358 and e0c63158 because the operable voltage range is different. power supply circuit oscillation system voltage regulator operating condition osc1 osc3 (2 mhz) v d1 (v) 1.3 2.1 0.9?.35 supply voltage v dd (v) 1.35?.2 2.2?.6 3.6?.5 v c2 mode normal mode normal mode not allowed not allowed not allowed e0c63158 power supply circuit oscillation system voltage regulator operating condition osc1 osc3 (4 mhz) v d1 (v) 1.3 2.25 0.9?.4 supply voltage v dd (v) 1.4?.3 2.3?.6 3.6?.5 v c2 mode normal mode normal mode not allowed not allowed not allowed e0c63358 power supply circuit oscillation system voltage regulator operating condition osc1 osc3 (4 mhz) v d1 (v) 2.05 v dd 0.9?.4 supply voltage v dd (v) 1.4?.7 2.7?.6 3.6?.5 normal mode not allowed normal mode not allowed E0C63P366 * the E0C63P366 does not enter the v c2 mode. the internal circuits of the e0c63358 and e0c63158 operate with the oscillation system regulated voltage (v d1 ). the E0C63P366 internal circuits operate with the supply voltage (v dd ).
8 E0C63P366 3) power supply terminal for the oscillation circuit (v d1 ) the v d1 voltage that is generated by the internal voltage regulator is used only for the osc1 oscillation circuit to stabilize the oscillation. as explained in item 1 above, the vdc register (ff00h?d0) does not affect the v d1 output voltage. 4) operating mode of lcd system voltage regulator the operable voltage range is different. e0c63358: v dd = 0.9v to 1.4v v c1 = v dd v dd = 1.4v to 3.6v v c1 = 1.05v (typ.) E0C63P366: v dd = 2.7v to 5.5v v c2 = 2.10v (typ.) * the E0C63P366 operation is guaranteed within the above voltage range. 5) operating mode of a/d converter power supply the a/d converter operating mode range of the E0C63P366 is different from that of the e0c63358 and e0c63158 because the operable voltage range is different. circuit a/d converter 0.9?.2 supply voltage v dd (v) 2.2?.6 3.6?.5 v c2 mode normal mode not allowed e0c63158 circuit a/d converter 0.9?.6 supply voltage v dd (v) 1.6?.6 3.6?.5 v c2 mode normal mode not allowed e0c63358 circuit a/d converter 0.9?.7 supply voltage v dd (v) 2.7?.6 3.6?.5 not allowed normal mode E0C63P366 l initial reset when the power is turned on, the reset terminal must be set at low level until the supply voltage becomes 2.7v or more. v dd reset 2.0 msec or more 2.7 v 0.5? dd 0.1? dd or less (low level) power on E0C63P366 uses the initial reset signal as a trigger for setting either the normal operation mode or the program- ming mode. therefore, design the reset input circuit so that the ic will be reset for sure. initial resetting during operation is the same as the e0c63158. when resetting the ic in the normal operation mode, make sure to fix the sprg terminal at high level. l rom, ram the E0C63P366 employs a flash eeprom for the internal rom. the flash eeprom can be rewritten up to 10 times. rewriting data is done at the user's own risk. 1) code rom the built-in code rom is a flash rom for loading programs, and has a capacity of 16,384 steps 13 bits. the core cpu can linearly access the program space up to step ffffh from step 0000h, however, the program area of the E0C63P366 is step 0000h to step 3fffh. the program start address after initial reset is assigned to step 0110h. the non-maskable interrupt (nmi) vector and hardware interrupt vectors are allo- cated to step 0100h and steps 0102hC010eh, respectively.
9 E0C63P366 note: pay attention to the application program size since the code rom of the e0c63358/e0c63158 is smaller (8,192 steps 13 bits, 0000hC1fffh) than that of the E0C63P366. 0000h 3fffh 4000h ffffh 0000h 0100h 0102h 010eh 0110h program area nmi vector hardware interrupt vectors program start address program area prom unused area 13 bits e0c63000 core cpu program space E0C63P366 program area 2) ram the ram is a data memory for storing various kinds of data, and has a capacity of 2,048 words 4 bits. the ram area is assigned to addresses 0000h to 07ffh on the data memory map. addresses 0100h to 01ffh are 4-bit/16-bit data accessible areas and in other areas it is only possible to access 4-bit data. when programming, refer to the "technical manual" of the e0c63358 or e0c63158. note: pay attention to the application data size since the ram of the e0c63358/e0c63158 is smaller (512 words 4 bits) than that of the E0C63P366. 0000h 00ffh 0100h 01ffh 0200h 07ffh 4 bits 4-bit access area (sp2 stack area) 4-bit access area (data area) 4/16-bit access area (sp1 stack area) l oscillation circuit in the E0C63P366, only crystal oscillation is available for the osc1 oscillation circuit and either ceramic or cr oscillation is available for the osc3 oscillation circuit. furthermore, pay attention to the difference on the oscilla- tion start time according to the supply voltage. be sure to have enough margin especially for stabilizing the osc3 oscillation when controlling the peripheral circuit that uses the osc3 clock. * the E0C63P366 has differences in its production process from the mask rom models (e0c63358 and e0c63158). the constant must be decided according to the characteristics of the mask rom model.
10 E0C63P366 l svd circuit the E0C63P366 has a built-in svd (supply voltage detection) circuit the same as the e0c63358 and e0c63158. however, the detection levels are different from those of the e0c63358 and e0c63158. furthermore, there is a great restriction on the operable detection levels in the E0C63P366. when using the svd function, check the available detection level. detection level svds3? = "0" svds3? = "1" svds3? = "2" svds3? = "3" svds3? = "4" svds3? = "5" svds3? = "6" svds3? = "7" svds3? = "8" svds3? = "9" svds3? = "10" svds3? = "11" svds3? = "12" svds3? = "13" svds3? = "14" svds3? = "15" min. 0.95 1.05 1.10 1.15 1.20 1.25 1.35 1.55 1.90 1.95 2.00 2.05 2.15 2.25 2.45 2.55 typ. 1.05 1.10 1.15 1.20 1.25 1.30 1.40 1.60 1.95 2.00 2.05 2.10 2.20 2.30 2.50 2.60 max. 1.15 1.15 1.20 1.25 1.30 1.35 1.45 1.65 2.00 2.05 2.10 2.15 2.25 2.35 2.55 2.65 e0c63158 min. typ. max. 2.50 2.60 2.70 2.80 2.90 3.00 E0C63P366 not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed not allowed min. 0.95 1.02 1.07 1.12 1.16 1.21 1.30 1.49 1.81 1.86 1.91 1.95 2.05 2.14 2.33 2.42 typ. 1.05 1.10 1.15 1.20 1.25 1.30 1.40 1.60 1.95 2.00 2.05 2.10 2.20 2.30 2.50 2.60 max. 1.15 1.18 1.23 1.28 1.34 1.39 1.50 1.71 2.09 2.14 2.19 2.25 2.35 2.46 2.68 2.78 e0c63358 a criteria voltage can be set using the svds0Csvds3 register (i/o memory address: ff04h). since the minimum operating voltage of the E0C63P366 is 2.7v, 2.7v or less criteria voltages are not available. be aware that the svd circuit in the E0C63P366 may not operate when a 2.7v or less criteria voltage is selected. for the software control sequence of the svd circuit, refer to the technical manual of the e0c63358 and e0c63158. n electrical characteristics note: the electrical characteristics of the E0C63P366 are different from those of the e0c63358/e0c63158. the following characteristic values should be used as reference values when the E0C63P366 is used as a development tool. l absolute maximum ratings rating supply voltage input voltage (1) input voltage (2) permissible total output current * 1 operating temperature storage temperature * 2 soldering temperature / time permissible dissipation * 3 * 1: * 2: * 3: ( v ss =0v ) symbol v dd v i v iosc s i vdd topr tstg tsol p d value -0.5 to 7.0 -0.5 to v dd + 0.3 -0.5 to v d1 + 0.3 10 -20 to 70 -65 to 150 260 c, 10sec ( lead section ) 250 the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pin (or is drawn in). the storage temperature cannot guarantee data holding capability. in case of plastic package (qfp15-100pin). unit v v v ma c c mw l recommended operating conditions condition supply voltage oscillation frequency ( ta=-20 to 70 c ) symbol v dd av dd f osc1 f osc3 unit v v khz khz khz max. 5.5 5.5 4100 typ. 3.0 3.0 32.768 1800 min. 2.7 2.7 remark v ss =0v normal mode av ss =0v crystal oscillation cr oscillation ceramic oscillation
11 E0C63P366 l dc characteristics characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c3 are internal voltage, c 1 ? 5 =0.2 f) symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 unit v v v v a a a ma ma ma ma a a a a a a max. v dd v dd 0.2? dd 0.1? dd 0.5 0 -5 -1.5 -1.5 -10 -10 -220 typ. -10 min. 0.8? dd 0.9? dd 0 0 0 -0.5 -16 3 3 10 10 220 condition k00?3, k10?3, k20, p00?3, p10?3, p20?3 p30?3, p40?3, rxd, sclk, clkin, sprg reset, test k00?3, k10?3, k20, p00?3, p10?3, p20?3 p30?3, p40?3, rxd, sclk, clkin, sprg reset, test v ih =3.0v k00?3, k10?3, k20, p00?3, p10?3, p20?3 p30?3, p40?3, rxd, sclk, clkin, sprg reset, test v il1 =v ss k00?3, k10?3, k20, p00?3 no pull-up p10?3, p20?3, p30?3, p40?3 v il2 =v ss k00?3, k10?3, k20, p00?3, p10?3, p20?3 with pull-up p30?3, p40?3, rxd, sclk, clkin, sprg reset, test v oh1 =0.9? dd r00?3, r10?3, r20?3, p00?3, p10?3 p20?3, p30?3, p40?3, txd, sclk v oh2 =0.9? dd bz v ol1 =0.1? dd r00?3, r10?3, r20?3, p00?3, p10?3 p20?3, p30?3, p40?3, txd, sclk v ol2 =0.1? dd bz v oh3 =v c5 -0.05v com0? v ol3 =v ss +0.05v v oh4 =v c5 -0.05v seg0?1 v ol4 =v ss +0.05v v oh5 =0.9? dd seg0?1 v ol5 =0.1? dd characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) high level output current (1) high level output current (2) low level output current (1) low level output current (2) common output current segment output current (during lcd output) segment output current (during dc output) (unless otherwise specified: v dd =5.0v, v ss =0v, f osc1 =32.768khz, ta=25 c, v d1 /v c1 /v c2 /v c3 are internal voltage, c 1 ? 5 =0.2 f) symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i oh1 i oh2 i ol1 i ol2 i oh3 i ol3 i oh4 i ol4 i oh5 i ol5 unit v v v v a a a ma ma ma ma a a a a a a condition k00?3, k10?3, k20, p00?3, p10?3, p20?3 p30?3, p40?3, rxd, sclk, clkin, sprg reset, test k00?3, k10?3, k20, p00?3, p10?3, p20?3 p30?3, p40?3, rxd, sclk, clkin, sprg reset, test v ih =5.0v k00?3, k10?3, k20, p00?3, p10?3, p20?3 p30?3, p40?3, rxd, sclk, clkin, sprg reset, test v il1 =v ss k00?3, k10?3, k20, p00?3 no pull-up p10?3, p20?3, p30?3, p40?3 v il2 =v ss k00?3, k10?3, k20, p00?3, p10?3, p20?3 with pull-up p30?3, p40?3, rxd, sclk, clkin, sprg reset, test v oh1 =0.9? dd r00?3, r10?3, r20?3, p00?3, p10?3 p20?3, p30?3, p40?3, txd, sclk v oh2 =0.9? dd bz v ol1 =0.1? dd r00?3, r10?3, r20?3, p00?3, p10?3 p20?3, p30?3, p40?3, txd, sclk v ol2 =0.1? dd bz v oh3 =v c5 -0.05v com0? v ol3 =v ss +0.05v v oh4 =v c5 -0.05v seg0?1 v ol4 =v ss +0.05v v oh5 =0.9? dd seg0?1 v ol5 =0.1? dd max. v dd v dd 0.2? dd 0.1? dd 0.5 0 -10 -3 -3 -10 -10 -660 typ. -15 min. 0.8? dd 0.9? dd 0 0 0 -0.5 -25 6 6 10 10 660
12 E0C63P366 l analog circuit characteristics and current consumption svd voltage svd circuit response time current consumption * 1: v svd t svd i op v s a a a ma ma 2.90 3.00 100 6 60 200 0.9 1.2 2.70 2.80 2.5 37 120 0.6 0.8 2.50 2.60 without panel load. the svd circuit and the a/d converter are off. av ref is open. svds0?="0" svds0?="1" svds0?="2" svds0?="3" svds0?="4" svds0?="5" svds0?="6" svds0?="7" svds0?="8" svds0?="9" svds0?="10" svds0?="11" svds0?="12" svds0?="13" svds0?="14" svds0?="15" during halt 32.768khz normal mode lcd power off during halt 32.768khz normal mode * 1 lcd power on during execution 32.768khz (crystal oscillation) normal mode * 1 1.8mhz (cr oscillation) lcd power on 4mhz (ceramic oscillation) characteristic lcd drive voltage symbol v c1 v c2 v c3 unit v v v max. 1/2? c2 -0.1 typ. 1.12 3/2? c2 typ. 2.10 min. 1/2? c2 0.95 typ. 0.88 3/2? c2 0.95 condition connect 1m w load resistor between v ss and v c1 (without panel load) connect 1m w load resistor between v ss and v c2 (without panel load) connect 1m w load resistor between v ss and v c3 (without panel load) (unless otherwise specified: v dd =3.0v, v ss =0v, f osc1 =32.768khz, c g =25pf, ta=25 c, v d1 /v c1 /v c2 /v c3 are internal voltage, c 1 ? 5 =0.2 f) a/d converter characteristics characteristic resolution error convertion time input voltage reference voltage av ref resistance symbol t conv av ref unit bit lsb lsb s s v v k w max. 8 3 3 10.5 641 av ref av dd typ. 8 50 min. 8 -3 -3 av ss 0.9 15 condition 3.6v v dd 5.5v fconv=osc3/2 or osc1 2.7v v dd 3.6v fconv=osc3/2 or osc1 fconv=osc3/2=2mhz fconv=osc1=32khz (unless otherwise specified: av dd =v dd =2.7 to 3.6v, av ss =v ss =0v, ta=-25 to 75 c)
13 E0C63P366 n package l package dimensions plastic qfp15-100pin unit: mm l pin layout no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pin name E0C63P366 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 e0c63358 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pin name E0C63P366 clkin sprg com0 com1 com2 com3 cb ca v c3 v c2 v c1 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test av ref av dd av ss rxd txd e0c63358 n.c. n.c. com0 com1 com2 com3 cb ca v c3 v c2 v c1 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test av ref av dd av ss n.c. n.c. no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pin name E0C63P366 sclk p43 p42 p41 p40 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r23 r22 r21 r20 e0c63358 n.c. p43 p42 p41 p40 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r23 r22 r21 r20 no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pin name E0C63P366 r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 seg0 seg1 seg2 seg3 seg4 seg5 seg6 e0c63358 r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 seg0 seg1 seg2 seg3 seg4 seg5 seg6 n.c. : no connection 14 0.1 16 0.4 51 75 14 0.1 16 0.4 26 50 index 0.18 25 1 100 76 1.4 0.1 0.1 1.7 max 1 0.5 0.2 0 10 0.125 +0.05 ?.025 0.5 +0.1 ?.05
14 E0C63P366 l pin aassignment comparison list (E0C63P366: qfp15-100pin, e0c63158: qfp12-48pin) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 no. E0C63P366 e0c63158 E0C63P366 e0c63158 E0C63P366 e0c63158 E0C63P366 e0c63158 pin name seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 pin name no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 no. 11 12 13 1 2 3 4 5 6 7 8 9 10 pin name clkin sprg com0 com1 com2 com3 cb ca v c3 v c2 v c1 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test av ref av dd av ss rxd txd pin name ?( * 1) ?( * 1) cb ca v c2 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test v ref ?( * 1) ?( * 1) no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 no. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 pin name sclk p43 p42 p41 p40 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r23 r22 r21 r20 pin name ?( * 1) p43 p42 p41 p40 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 no. 30 31 32 33 34 35 37 38 39 40 41 42 43 44 45 46 47 48 pin name r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 seg0 seg1 seg2 seg3 seg4 seg5 seg6 pin name r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 * 1 : pin for serial programming l pin aassignment comparison list (E0C63P366: qfp15-100pin, e0c63158: qfp13-64pin) no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 no. E0C63P366 e0c63158 E0C63P366 e0c63158 E0C63P366 e0c63158 E0C63P366 e0c63158 pin name seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 pin name no. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 no. 13 14 15 1 2 3 4 5 6 7 8 9 12 10 11 pin name clkin sprg com0 com1 com2 com3 cb ca v c3 v c2 v c1 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test av ref av dd av ss rxd txd pin name ?( * 1) ?( * 1) cb ca v c2 v ss osc1 osc2 v d1 osc3 osc4 v dd reset test v ref av dd av ss ?( * 1) ?( * 1) no. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 no. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pin name sclk p43 p42 p41 p40 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r23 r22 r21 r20 pin name ?( * 1) p43 p42 p41 p40 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r23 r22 r21 r20 no. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 no. 41 42 43 44 45 46 52 53 54 55 56 57 58 59 60 61 62 63 pin name r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 seg0 seg1 seg2 seg3 seg4 seg5 seg6 pin name r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 * 1 : pin for serial programming
15 E0C63P366 n pin description pin name v dd v ss v d1 v c1 , v c3 v c2 ca, cb osc1 osc2 osc3 osc4 k00?03 k10?13 k20 p00?03 p10?13 p20?23 p30?33 p40?43 r00 r01 r02 r03 r10?13 r20?23 com0?om3 seg0?eg31 av dd av ss av ref bz reset test rxd * 2 txd * 2 sclk * 2 clkin * 2 sprg * 2 function power (+) supply pin power (? supply pin internal regulated voltage output pin unused unused * 1 lcd system boosting capacitor connecting pin osc1 oscillation input pin osc1 oscillation output pin osc3 oscillation input pin osc3 oscillation output pin input port input port input port i/o port i/o port i/o port i/o port i/o port output port output port output port/tout output output port/fout output output port output port unused unused power (+) supply pin for a/d converter power (? supply pin for a/d converter reference voltage for a/d converter buzzer output pin initial reset input pin testing input pin unused (high) unused unused (high) unused (high) unused (high) function power (+) supply pin power (? supply pin internal regulated voltage output pin unused unused unused osc1 oscillation input pin osc1 oscillation output pin unused unused unused (high or low) unused (high or low) unused (high or low) unused (high or low) unused (high or low) unused (high or low) unused (high or low) unused (high or low) unused unused unused unused unused unused unused unused unused unused unused unused initial reset input pin unused (high) prom serial programming data input pin prom serial programming data output pin prom serial programming clock input pin prom serial programming source clock input pin prom serial programming mode setting pin pin no. 43 37 40 36, 34 35 33, 32 38 39 41 42 85?8 89?2 93 71?8 67?4 63?0 59?6 55?2 83 82 81 80 79?6 75?2 28?1 94?00, 1?5 47 48 46 84 44 45 49 50 51 26 27 normal operation mode serial programming mode in/out i o i o i i i i/o i/o i/o i/o i/o o o o o o o o o o i i i o i i i in/out i o i o i i i i i i i i o o o o o o o o o i i i o i/o i i * 1: the oscillation system voltage regulator and the a/d converter power supply circuit do not enter v c2 mode. * 2: pin for serial programming in the parallel programming mode, all the terminals are set to the appropriate status by the exclusive prom writer.
16 E0C63P366 n pad layout l diagram of pad layout x y (0, 0) 5.80 mm 5.80 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 die no. 102 l pad coordinates no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pad name r13 r12 r11 r10 r03 r02 r01 r00 bz k00 k01 k02 k03 k10 k11 k12 k13 k20 n.c. seg0 seg1 seg2 seg3 seg4 seg5 seg6 x 2,309 2,126 1,943 1,760 1,577 1,394 1,211 1,028 845 662 479 296 113 -71 -254 -437 -620 -803 -986 -1,167 -1,292 -1,487 -1,611 -1,806 -1,931 -2,126 y 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 no. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 pad name seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 clkin x -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,361 y 2,079 1,839 1,715 1,482 1,357 1,125 1,000 767 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,757 -2,361 no. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 pad name sprg com0 com1 com2 com3 cb ca v c3 v c2 v c1 v ss osc1 osc2 v d1 osc3 osc4 v dd n.c. reset test av ref av dd av ss rxd txd sclk x -2,171 -1,980 -1,790 -1,599 -1,409 -1,218 -1,028 -837 -647 -456 -266 -83 116 306 497 687 878 993 1,184 1,374 1,565 1,755 1,946 2,136 2,327 2,759 y -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,759 -2,346 no. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 pad name p43 p42 p41 p40 p33 p32 p31 p30 p23 p22 p21 p20 p13 p12 p11 p10 p03 p02 p01 p00 r23 r22 r21 r20 x 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 2,759 y -2,147 -1,946 -1,745 -1,544 -1,346 -1,148 -950 -752 -554 -356 -158 41 239 437 635 833 1,031 1,229 1,427 1,625 1,823 2,021 2,219 2,417 n.c. : no connection unit: m
17 E0C63P366 n basic external connection diagram 1 v ss 2 txd 3 rxd 4 clk 5 sclk 6 v ss 7 clkw 8 v pp exclusive prom writer exclusive cable ca cb av dd av ref test v dd v d1 osc1 osc2 osc3 osc4 reset v ss av ss c 1 c 2 c gx c dc c res c p 2.7 v | 5.5 v + x'tal cr * 3 * 2 r cr * 1 k00?03 k10?13 k20 p00?03 p10 (sin) p11 (sout) p12 (sclk) p13 (srdy) p20?23 p30?33 p40 (ad0) p41 (ad1) p42 (ad2) p43 (ad3) r00 r01 r02 (tout) r03 (fout) r10?13 r20?23 sprg txd rxd clkin sclk seg0 | seg31 com0 | com3 c gc bz piezo coil input i/o output c 3 c 4 c 5 v v v c1 c2 c3 x'tal c gx cr c gc c dc r cr c 1 ? 5 c p c res crystal oscillator trimmer capacitor ceramic oscillator gate capacitor drain capacitor resistor for osc3 cr oscillation capacitor capacitor reset terminal capacitor 32.768 khz, c i (max.) = 34 k w 5?5 pf 4 mhz (3.0 v) 100 pf 100 pf 91 k w (1.8 mhz/3.0 v) 0.2 f 3.3 f 0.1 f lcd panel 32 4 E0C63P366 [the potential of the substrate (back of the chip) is v ss .] * 1: crystal oscillation * 2: cr oscillation * 3: ceramic oscillation when used as the e0c63358 (leave open when used as the e0c63158) note: the above table is simply an example, and is not guaranteed to work.
E0C63P366 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110 http://www.epson.co.jp/device/ n epson electronic devices website

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